1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating a semiconductor wafer capable of achieving a mass production of silicon-on-insulator (SOI) devices while reducing manufacturing costs and improving the productivity and throughput.
2. Description of the Prior Art
In the fabrication of semiconductor devices, formation of an SOI structure is involved to achieve an isolation between adjacent elements, thereby obtaining a superior electrical characteristic. Such an SOI structure is made by forming a silicon oxide film as an insulator on an under silicon substrate and forming another silicon substrate (to be used as an active substrate), for example, a single-crystalline silicon layer on the silicon oxide film. By virtue of an easy element isolation and a superior electrical characteristic of the SOI structure, a number of research efforts have been made in association with SOI semiconductor wafer formation techniques.
Generally, bulk metal oxide semiconductor field effect transistors (MOSFET's) have a 4-terminal structure consisting of a gate, a source, a drain and a silicon substrate. However, MOSFET's having an SOI structure do not require connection of contacts and associated lines to the silicon substrate, as differently from the bulk MOSFET's. Accordingly, MOSFET's having an SOI structure have a 3-terminal structure consisting of a gate, a source and a drain so that they can have a compact chip size.
In the fabrication of CMOS devices using MOSFET's having the above-mentioned SOI structure, it is unnecessary to form wells. In this case, neighboring active regions of MOSFET's are insulated from one another. Accordingly, it is possible to prevent the occurrence of a latch-up phenomenon.
In the case of an SOI device fabricated on a silicon thin film having a small thickness, its source/drain junction is formed throughout the thickness of the silicon thin film. The source/drain has little area junction capacitance. In this case, only a perimeter junction capacitance exists.
In this regard, SOI devices exhibit high-speed low-power consumption characteristics, as compared to bulk MOSFET's.
In addition, SOI wafers reduce a capacitive coupling occurring between the circuit elements of the entire IC chip and the latch-up of the CMOS circuit while reducing the chip size and increasing the packing density, thereby increasing the operating speed of the entire circuit. It is also possible to reduce a generation of parasitic capacitance.
Furthermore, SOI wafers have advantages such as a reduction in the hot electron effect and a reduction in the short channel effect.
Meanwhile, SOI wafers are mainly fabricated using a bond and etch (BE) method or a separation by implanted oxygen (SIMOX) method. In accordance with the BE method, two wafers are bonded to each other, and one of the bonded wafers is processed to have a reduced thickness. In accordance with the SIMOX method, oxygen is implanted in the semiconductor substrate. The oxygen-implanted semiconductor substrate is then annealed, thereby forming a buried oxide film and a silicon film. Recently, a smart cut method has been used in some cases.
Now, a conventional method for fabricating an SOI wafer will be described in conjunction with FIGS. 1 to 5.
FIGS. 1 to 5 are sectional views respectively illustrating sequential steps of the conventional SOI wafer fabrication method which uses a conventional smart cut method.
In accordance with the conventional method, a first wafer 1 and a second wafer 11 are first prepared, as shown in FIG. 1. A thermal oxide film 3 is then formed to a desired thickness over the first wafer 1.
Thereafter, hydrogen ions are implanted in the first wafer 1, thereby forming a hydrogen ion-implanted region 5 deeper than the thermal oxide film 3, as shown in FIG. 2.
The implantation of hydrogen ions is carried out using ion implantation energy of 10 KeV to 2 MeV and a dose of 1.times.10.sup.16 /cm.sup.2 to 1.times.10.sup.17 /cm.sup.2.
The first wafer 1 is subsequently bonded to the second wafer 12 which is a bare wafer, as shown in FIG. 3. At this time, the thermal oxide film 3 formed over the first wafer 1 is bonded to the upper surface of the second wafer 11.
The resulting structure, in which the first and second wafers 1 and 11 are bonded to each other, is annealed at a temperature of about 400 to 600.degree. C.
As shown in FIG. 4, the resulting structure is cut along its portion where the hydrogen ion-implanted region 5 is formed, thereby dividing it into an SOI wafer including the second wafer 11 and a bare wafer including the first wafer 1.
The SOI wafer 10 also includes the thermal oxide film 3 disposed over the second wafer 11 and the cut portion of the first wafer 1 disposed over the thermal oxide film 3 in a bonded state.
The SOI wafer 10 is annealed at a high temperature of 900.degree. C. or above so that it has a strengthened chemical coupling property. The SOI wafer 10 is also subjected to a touch polishing using a chemical mechanical polishing (CMP) device so that the roughness of its surface is reduced. Thus, an SOI wafer capable of achieving an easy fabrication of semiconductor devices at subsequent steps is obtained.
However, the above-mentioned conventional method has various problems, as shall be described.
In accordance with the conventional method, an SOI wafer is fabricated by implanting hydrogen ions in a wafer formed with a thermal oxide film, bonding a bare wafer to the hydrogen ion-implanted wafer, and cutting the resulting structure into an SOI wafer portion and a bare wafer portion along the hydrogen ion-implanted portion.
Since the SOI wafer fabricated in the above-mentioned manner has a rough surface, it is required to perform a polishing process in order to reduce the surface roughness of the wafer. The remaining bare wafer is reused to fabricate an SOI wafer.
However, where an SOI wafer is fabricated by reusing the above-mentioned remaining bare wafer, the fabrication process is complicated, thereby increasing costs. In this case, it is also impossible to achieve mass production.